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  1. Dec 10, 2021
    • Geo Ster's avatar
      Groundwork for IOP DMA implementation · 1cce9b6f
      Geo Ster authored
      * The DMA routine on the IOP works similarly to the PSX version with a
      few additions. There are 7 channels from the PSX and an additional 6 new
      PS2 exclusive ones. One the PSX, each channel has 3 registers used
      to configure and use it and 3 global registers.
      
      * The PS2 contains all the older DMA registers, but it add 6 more channels
      and duplicates the global registers (DPCR now has a counterpart called DPCR2)
      This is done because each global register can control up to 7 channels.
      An additional register on each channel (tadr) and 2 additional
      global registers have been added as well. For now we don't really
      care to implement them, only read/write to them.
      
      * For reading and writing to the registers structs are used to prevent
      the usage of switch and if statements.
      1cce9b6f
  2. Dec 02, 2021
  3. Nov 30, 2021
    • Geo Ster's avatar
      Introducing the IOP · 1d16fdad
      Geo Ster authored
      * So after a week, it's finally here! The initial implementation of the
      IOP has been added to the emulator. You might wonder why did it take so
      long? This was mostly because I wanted to make the implementation as complete
      as possible and also test it to ensure it's bug free. So this is actually
      based on the MIPS R3000A interpreter I wrote last year for my PS1 emulator.
      So did I just copy the code and call it a day? Hell no, the code in that
      ancient project is awful, even if it works. So I completely rewrote the
      interpreter by using our modern techiniques of storing state. So rewriting the old
      code allowed me to test if it actually worked in that environment
      and could boot PSX games.
      
      * Due to this, the implementation is a bit more complete than the EE
      as it includes interrupt support. In addition we have to account for
      the fact that the IOP runs at 36.864MHz, in constrast to the EE which
      clocks at 295MHz. This maps approximatly to an 1/8 ratio, which means
      that 1 IOP instruction will run every 8 EE cycles. The current implementation
      of this is hacky and a bit inaccurate because some EE instructions
      can take more than 1 cycle to execute, but it's good enough for now
      (Play! assumes this as well and can boot 40%+ of games).
      
      * Because both the CPU emulators can share a lot of naming conventions,
      to avoid confusion each processor has been seperated into a namespace
      so we can always know which CPU we are refering to. Finally, for now
      reads/writes except for the BIOS and IOP RAM, haven't been implemented
      but will come soon.
      1d16fdad
  4. Nov 16, 2021
    • Geo Ster's avatar
      Wrap log funtion into a macro and implement BIOS console · c4c3a1ff
      Geo Ster authored
      * Since log output is getting very large, it's common to have to wait
      5+ minutes before any unknow instruction is encoutered. Printing to the
      console actually takes a lot of time and slows down interpretation
      significantly. Right now we don't care, since we just want to boot the BIOS
      but let's have an option to disable all the log messages if we want.
      
      * In addition record all writes to 0xb000f180 which is the BIOS console
      output address, so we can have some output, which will be very useful
      c4c3a1ff
  5. Nov 15, 2021
    • Geo Ster's avatar
      Add more shift (SRA/SLL) instructions · 49cabc82
      Geo Ster authored
      * Now the BIOS enters another infinite loop. However that seems to be
      normal, as it's waiting for COP0_REG[9], the timer which we haven't
      implemented yet. I think it's also time to add support for interrupts as
      well since these go hand in hand with timers
      49cabc82
  6. Nov 14, 2021
    • Geo Ster's avatar
      Implement first FPU instruction · 9444ba92
      Geo Ster authored
      * Since we have encountered our first FPU register, add the 32 floating
      point registers to the CPU.
      
      * In addition solve a small bug in the JAL instruction related to the
      return link address. See previous commit for details
      9444ba92
    • Geo Ster's avatar
      Move header files to src dir · 9969bd6f
      Geo Ster authored
      * Having the header files in a seperate dir is only useful when developing
      libraries that are meant to be used by other programs. In our case though
      it makes the file structure more tedious so gather everything in one place.
      9969bd6f
  7. Nov 03, 2021
    • Geo Ster's avatar
      Implement ORI/ADDI/LQ · ebf1986d
      Geo Ster authored
      In addition:
      * Correct register notation (word refers to a 32bit quantity not 16bit)
      * Simplify sign extension casing
      * Add more useful logging
      ebf1986d
  8. Oct 31, 2021
    • Geo Ster's avatar
      Add initial EE/Bus implementations · 2ad0640f
      Geo Ster authored
      * This commit adds a most basic CPU class that acts as a template
      which we will slowly build.
      
      * The architecture is pretty simple; the ComponentManager will create all
      the seperate components (EE, VP, IOP, GS etc) as unique_ptr's since
      it owns them and only it has access to them. All the other components
      must pass through the manager to read/write data to memory.
      To achieve this they are given a pointer to the ComponentManger in their constructor.
      
      * For now the CPU directly accesses the bios which shouldn't
      happen but will be fixed eventually when I implement generic
      read/writes. The goal is to start implementing the CPU as fast as
      possible in order to get to the GPU/VPU's and display something!
      2ad0640f
    • Geo Ster's avatar
      Initial commit · 9c39208d
      Geo Ster authored
      * This is the beginning of a surely arduous journey of semi-correctly emulating
      the PS2 the flagship console from Sony in 2001. The console was chosen
      for it's impressive performance at the time, relatively simple MIPS architecture
      compared to the PowerPC (Gamecube) and x86 (Xbox) competitors at the time, and because
      I own one since I wouldn't want to be caught doing piracy on an open source
      competition...
      
      The PS2 also has a myriad of resources available including comprehensive CPU documentation
      for it's MIPS ISA which will be used in the development of this emulator. Any sources that I use, will be referenced
      in the coresponding commits for the judges to look at. For development hardware documentation and info from real emulators will be used
      (I'll try to avoid using code from other projects as much as possible though).
      I've also done a PS1 emulator in the past so the minor similarities in architecture
      will help speed this process up a little.
      
      For now this is just a window with glfw and a ready opengl context.
      I hope it will be able to boot the PS2 soon enough though...
      9c39208d
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