* The DMA routine on the IOP works similarly to the PSX version with a
few additions. There are 7 channels from the PSX and an additional 6 new
PS2 exclusive ones. One the PSX, each channel has 3 registers used
to configure and use it and 3 global registers.

* The PS2 contains all the older DMA registers, but it add 6 more channels
and duplicates the global registers (DPCR now has a counterpart called DPCR2)
This is done because each global register can control up to 7 channels.
An additional register on each channel (tadr) and 2 additional
global registers have been added as well. For now we don't really
care to implement them, only read/write to them.

* For reading and writing to the registers structs are used to prevent
the usage of switch and if statements.

* Due to load delay slots the target register doesn't get
written immediately, so use the value instead to correctly
display the loaded value in the logs

* Nothing to really say here, just looks better imo

* On reads/writes it is important to check the address alignment before
proceeding with the operation. However unalignment errors almost
never happen in real world games, so let the compiler know that these
branches are unlikely to happen to speed them up a bit.

* So after a week, it's finally here! The initial implementation of the
IOP has been added to the emulator. You might wonder why did it take so
long? This was mostly because I wanted to make the implementation as complete
as possible and also test it to ensure it's bug free. So this is actually
based on the MIPS R3000A interpreter I wrote last year for my PS1 emulator.
So did I just copy the code and call it a day? Hell no, the code in that
ancient project is awful, even if it works. So I completely rewrote the
interpreter by using our modern techiniques of storing state. So rewriting the old
code allowed me to test if it actually worked in that environment
and could boot PSX games.

* Due to this, the implementation is a bit more complete than the EE
as it includes interrupt support. In addition we have to account for
the fact that the IOP runs at 36.864MHz, in constrast to the EE which
clocks at 295MHz. This maps approximatly to an 1/8 ratio, which means
that 1 IOP instruction will run every 8 EE cycles. The current implementation
of this is hacky and a bit inaccurate because some EE instructions
can take more than 1 cycle to execute, but it's good enough for now
(Play! assumes this as well and can boot 40%+ of games).

* Because both the CPU emulators can share a lot of naming conventions,
to avoid confusion each processor has been seperated into a namespace
so we can always know which CPU we are refering to. Finally, for now
reads/writes except for the BIOS and IOP RAM, haven't been implemented
but will come soon.