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    b591d341
    Add VU0 support · b591d341
    Geo Ster authored
    * The VUs are custom made SIMD processors used to accelerate
    math operations on vectors and matrices. This doesn't seem that
    bad but in reality they are probably the hardest piece of hardware
    on the PS2 to emulate correctly. That is for two reasons:
    
    1. Not much documentation
    2. Complex and confusing pipeline
    
    The first it pretty self explanatory. However the second reason,
    the pipeline is what makes them so hard. Normally, even in LLE
    emulators we don't care about the internal pipeline of the chips,
    as it doesn't affect the result of the instructions themselves,
    it just makes them run faster. The CPU doesn't expose its pipeline
    to the target program.
    
    Some architectures are different. MIPS for example has branch delay
    slots which in reality are a pipeline quirk. Generally the more
    pipeline quirks you expose to the program the more complex it is
    to emulate correctly. The VUs basically expose their full pipeline...
    
    For now we only support a portion of the macro mode instruction set.
    The pipeline is going to come when the VU starts executing micro programs
    and when I figure out how it works...
    b591d341
    History
    Add VU0 support
    Geo Ster authored
    * The VUs are custom made SIMD processors used to accelerate
    math operations on vectors and matrices. This doesn't seem that
    bad but in reality they are probably the hardest piece of hardware
    on the PS2 to emulate correctly. That is for two reasons:
    
    1. Not much documentation
    2. Complex and confusing pipeline
    
    The first it pretty self explanatory. However the second reason,
    the pipeline is what makes them so hard. Normally, even in LLE
    emulators we don't care about the internal pipeline of the chips,
    as it doesn't affect the result of the instructions themselves,
    it just makes them run faster. The CPU doesn't expose its pipeline
    to the target program.
    
    Some architectures are different. MIPS for example has branch delay
    slots which in reality are a pipeline quirk. Generally the more
    pipeline quirks you expose to the program the more complex it is
    to emulate correctly. The VUs basically expose their full pipeline...
    
    For now we only support a portion of the macro mode instruction set.
    The pipeline is going to come when the VU starts executing micro programs
    and when I figure out how it works...
vu0.cc 3.89 KiB