* This commit adds support for handling exceptions for our virtual
MIPS CPU. The implementation is based on the provided document's chapter
on Exception handling, and more specifically on the flowchart of level 1
exceptions (Section 5.1.1). To check if the current instruction is in a delay
slot we use a bool and cache it together with the currently executing instruction.

* The current implementation is only partially complete, since it's missing level 2
exception handling, but I reckon that those exceptions won't be needed
for a long time. This acts more as a foundation for implementing interrupts
which are 100% required for emulating even the most basic of systems.